Sigil

CSSL · Caveman Sigil Substrate Language
one source · CPU + GPU + console + mobile + web
28+ built-in effects · refinement types · source-to-source autodiff · Pony-6 capabilities · MLIR IR · Vulkan 1.4 + Level-Zero
Status Compiler in active development. Stage-0 scaffold stood up; parser + AST + HIR + 31/31 body-lower + F1 autodiff PROVEN (62/62) + HM foundation. 1,600+ tests, 0 clippy warnings, 6/6 commit gates. Session 4 in progress.

What is Sigil

Sigil is the shorthand; CSSLCaveman Sigil Substrate Language — is the full name. Same language. It is a single-source systems language that compiles to native x86-64 (AVX2 base + AVX-512 opportunistic) and SPIR-V (Vulkan 1.4 + Level-Zero), with backend stubs for D3D12, Metal, WebGPU, and consoles.

Four things distinguish it from the languages it draws from. First, the type system includes a Koka-style row-polymorphic effect system with 28+ built-in effects covering timing, power, thermal, backend gating, and IFC. Second, engine primitives — SDFs, Jets, render graphs, scenes — are compiler-aware built-ins, not library wrappers. Third, the non-negotiable feature set (autodiff, refinement types, effects, staging, IFC, observability) all ship in v1 rather than as "future work." Fourth, a set of bug patterns observed in prior game-engine work (Labyrinth of Apocalypse retrospective) were each mapped to a compile-time structural refusal — CSSL inverts "runtime safety" into "compile-time inexpressibility of the bug."

The language is currently pre-1.0. The compiler (compiler-rs/, 31 crates) is under active development. The specification (25 .csl files, ~200KB) is complete and frozen for v1. What follows is a reference to what the language is, grounded in the spec, with an honest note on what has shipped in the compiler versus what remains.

A Shader, Autodiff'd

An SDF shader in CSSL. Autodiff is a first-class operator (bwd_diff), not a library. The effect row on sdf_pixel says the function runs on GPU, under a 16ms deadline, emitting dispatch latency telemetry — the compiler discharges these statically where it can and asserts at runtime otherwise.

module com.apocky.examples.sdf_shader

use std::math::{vec3, length, normalize, dot, max}
use std::gpu::vec4

// Lipschitz-1 sphere SDF; F1-AD enabled.
@differentiable
@lipschitz(k = 1.0)
fn sphere_sdf(p : vec3, r : f32'pos) -> f32 {
    length(p) - r
}

@differentiable
fn scene_sdf(p : vec3) -> f32 {
    let d1 = sphere_sdf(p, 0.5)
    let d2 = sphere_sdf(p - vec3(1.0, 0.0, 0.0), 0.3)
    min(d1, d2)
}

// Normal via reverse-mode AD. bit-exact vs analytic central-differences.
fn surface_normal(hit_pos : vec3) -> vec3 {
    let g = bwd_diff(scene_sdf)(hit_pos).d_p
    normalize(g)
}

@fragment
fn sdf_pixel(uv : vec3) -> vec4
    / {GPU, Deadline<16ms>, Telemetry<DispatchLatency>}
{
    let cam_origin = vec3(0.0, 0.0, -3.0)
    let dir        = normalize(uv - cam_origin)
    let t          = ray_march(cam_origin, dir, 64)
    let hit        = cam_origin + dir * t
    let n          = surface_normal(hit)
    let lit        = max(dot(n, normalize(vec3(1.0, 1.0, -1.0))), 0.0)
    vec4(lit, lit, lit, 1.0)
}

Source: examples/sdf_shader.cssl in the CSSL repository. This compiles through HIR → MLIR → SPIR-V. The bwd_diff operator is lowered by source-to-source transformation on the structured MIR before SPIR-V emission.

The Non-Negotiable Six (F1–F6)

These are the features CSSL commits to shipping in v1. Each is referenced by ID throughout the specification (specs/00_MANIFESTO.csl).

F1 · AUTODIFF

Source-to-source differentiation

Slang.D surface syntax (@differentiable, fwd_diff, bwd_diff, IDifferentiable). Lowered on the structured MIR, not via LLVM-Enzyme — no LLVM dependency. Jet<T,N> higher-order native. Inverse rendering and inverse fluids as stdlib.

specs/05_AUTODIFF.csl · specs/17_JETS.csl
F2 · REFINEMENT TYPES

LiquidHaskell shape, SMT-backed

{v:T | P(v)} + tagged suffix T'tag. Discharged via Z3/CVC5 through the {Verify<method>} effect. Lipschitz proofs at compile time. Layout refinement: @layout(std140|std430|cpu|packed).

specs/03_TYPES.csl · specs/20_SMT.csl
F3 · EFFECT SYSTEM

Koka row-polymorphic, 28+ built-ins

Evidence-passing compilation (Xie+Leijen ICFP'21) lowers to plain-C-equivalent — zero runtime overhead. Effects cover resource, timing, determinism, hardware gating, power, thermal, IFC, audit, telemetry. Linear × handler integration via Eio-style one-shot resume.

specs/04_EFFECTS.csl · specs/12_CAPABILITIES.csl
F4 · STAGED COMPUTATION

Comptime, Futamura P3, macros

@staged + #run compile-time. Full Futamura P1+P2+P3 self-applicable partial evaluation. Racket-hygienic macros unified with staging. Shader permutations and DSL compilers emerge from the framework, not bespoke infrastructure.

specs/06_STAGING.csl · specs/13_MACROS.csl · specs/19_FUTAMURA3.csl
F5 · INFORMATION FLOW

Jif-DLM, structurally enforced

Decentralized Label Model: confidentiality + integrity labels threaded through every SSA value. Explicit declassification operators. Sensitive-domain labels, privilege tiers, compiler refuses harm-oriented effect compositions.

specs/11_IFC.csl
F6 · OBSERVABILITY

Native telemetry, signed audit

{Telemetry<scope>} effect; Level-Zero sysman-backed power, thermal, frequency on Intel. Signed audit chain via {Audit<dom>}. Test harness with nine oracle modes including differential-backend and replay.

specs/22_TELEMETRY.csl · specs/23_TESTING.csl

The Effect System

Effects are row-polymorphic (Koka lineage): ⟨e₁, e₂ | μ⟩ where μ is an inferred tail. A function's effect row declares its observable side-effects and hardware requirements; the compiler unions them with the caller's context and checks that the result is within the caller's declared bound.

28+ effects ship in v1. The categories below are from specs/04_EFFECTS.csl.

Built-in effects, by category
CategoryEffectsNotes
Resource / Timing {NoAlloc} {NoRecurse} {NoUnbounded} {Deadline<N>} {Realtime<p>} {Region<'r>} {Alloc} {Yield} {State<S>} {Exn<E>} {IO} Deadlines carry units (ns/μs/ms/s). Realtime priorities map to OS scheduler classes.
Determinism {DetRNG} {PureDet} {Reversible} PureDet is stricter than DetRNG: bit-exact cross-machine.
Hardware / Backend {CPU} {GPU} {XMX} {RT} {SIMD256} {SIMD512} {NUMA<n>} {Cache<l>} {Backend<api>} {Target<platform>} XMX = Intel matrix engine. Backends: Vulkan, LevelZero, D3D12, Metal, WebGPU, GNM, NVN.
Power / Thermal {Power<W>} {Thermal<°C>} Sysman-enforced on Intel via zesPowerSetLimits. Runtime guard + test oracle on other vendors.
IFC / Audit {Sensitive<dom>} {Audit<dom>} {Privilege<lvl>} {Verify<method>} {Telemetry<scope>} IFC labels + privilege tiers + signed chain via R18 ring buffer.

Discharge timing

Effects fall into three discharge buckets — how the compiler verifies them.

  • Compile-time only: {NoAlloc}, {NoRecurse}, {NoUnbounded}, {DetRNG}, {PureDet}, {Reversible}, {CPU/GPU/XMX/RT}, {SIMD*}, {NUMA/Cache}, {Backend/Target}, {Region}, {Sensitive/Privilege}.
  • Compile-time + runtime assert: {Deadline} (cost estimate + wallclock guard), {Power} (static model + sysman sample), {Thermal} (reject-if-overbudget + sysman sample), {Realtime}, {Verify} (SMT discharge), {Audit} (schema + signed-chain write), {Telemetry} (probe insertion + ring push).
  • Runtime only: user-defined handlers (State, Exn, Yield, custom).

Capability Model — Pony-6

Six reference capabilities control aliasing. This is Pony's model (not Austral's three), extended with Vale-style generational references for shared-mutable.

Capability matrix
CapMeaningTypical use
isoisolated, linear-mutableGPU buffers, command buffers, unique resources
trntransition (write-unique → freeze → read-many)build phase → immutable scene
refshared-mutable via 8-byte packed generational ref (Vale interop)entity handles, world references
valimmutable-sharedfrozen scene, const data, asset handles
boxread-only view over iso/trn/valquery interfaces, readers
tagopaque handle (no deref)Handle<T>, identity-only references

Linear values flowing through a handler permit one-shot resume only — a multi-shot resume on a linear value is a compile error. This is the Eio-OCaml5 pattern, production-proven, and is what makes fiber scheduling sound in the presence of exclusive resources.

Primary Hardware Target

CSSL is hardware-grounded: the v1 target is specified concretely, not abstractly. Other vendors work via SPIR-V portability; Intel gets the deep path because Level-Zero is a direct-to-metal compute and instrumentation API.

CPU · Intel 12–14 gen

  • x86-64-v3 base (AVX2 + FMA3 + BMI1/2 + POPCNT)
  • AVX-512 opportunistic runtime dispatch
  • Comptime emits both variants for hot kernels; fn-pointer table per-CPU
  • Pattern lineage: Highway + ISPC

GPU · Intel Arc A770

  • Xe-HPG DG2-512: 32 Xe-cores, 512 XVE, 512 XMX, 32 RT-cores
  • 17.2 TFLOPs FP32 / 137.6 TOPs FP16-XMX / 275.2 TOPs INT8-XMX
  • 16 GB GDDR6 · 560 GB/s · 16 MB L2 · 225 W TDP
  • Vulkan 1.4.333 + Level-Zero 1.14+

Backend surface

Backend capability matrix
Backend Graphics Compute RT XMX Scope
Vulkan 1.4 via coop portable primary
Level-Zero ✓✓ direct Intel compute + sysman
D3D12 via coop Windows
Metal coop Apple
WebGPU browser
GNM (PS5) / NVN (Switch 2) console stubs

Cooperative-matrix ops use KHR_cooperative_matrix (portable) preferred over SPV_INTEL_subgroup_matrix_multiply_accumulate. Ray-tracing uses VK_KHR_ray_query for inline-RT. Full extension inventory: specs/10_HW.csl.

Compilation Pipeline

.cssl source lex · parse HIR type check effect check IFC check
MIR (MLIR dialect) AD source-to-source staging / Futamura SMT discharge LIR
Cranelift → x86-64 (stage 0) bespoke x86-64 (stage 1+)
rspirv → SPIR-V → Vulkan / Level-Zero

Stage 0 uses Cranelift as a throwaway code generator to bootstrap. Stage 1+ replaces it with a bespoke x86-64 emitter owned by the project. No LLVM dependency anywhere in the pipeline. SPIR-V emission via rspirv from day one. MLIR Transform-dialect is used for pass scheduling (specs/15_MLIR.csl).

Bugs → Compiler Features

The design premise: the patterns that cause bugs in game-engine code are patterns the host language permits. CSSL inverts this — each known bug pattern is mapped to a structural refusal. From the Labyrinth of Apocalypse bug retrospective (specs/00_MANIFESTO.csl):

Bug pattern → compiler feature mapping
Bug patternCompile-time refusal
Central-diff perf cliff in SDF normalsF1 autodiff + source-to-source MIR
CPU/GPU SDF divergenceF3 effect rows {GPU}|{CPU}|⟨⟩-pure
Thin-SDF ray-march crashF2 refinement SDF'L<k≤1>
Audio callback heap allocF3 {NoAlloc} + {Deadline<N>}
GPU struct padding mismatchF2 @layout(std140|std430|cpu)
Hot-loop deadline missF3 {Deadline<N>} + {Realtime<p>}
Stale entity referencesHandle<T> generational-packed u64
Replay non-determinismF3 {DetRNG} + {PureDet}
Power regressionF3 {Power<W>} + R18 telemetry
Thermal throttleF3 {Thermal<°C>} + sysman enforcement
Unreproducible buildC99 anchor from stage-0 + signed audit

Dual Surface Syntax

CSSL has two parseable surfaces that share one HIR: a Rust-hybrid form (external-facing, familiar keywords, good for docs and onboarding) and a CSL-native form (primary, compressed, optimized for token density). Both parse to the same intermediate representation; a formatter round-trips losslessly between ASCII and Unicode glyphs.

The effect row after / is the signature's observable side-effects. A pure function omits it. Capability keywords (iso, trn, ref, val, box, tag) are first-class type constructors.

// effect system: declare what a function observes.
fn render_scene<S : Scene>(cam : Camera) -> Image
    / {GPU, Deadline<16ms>, NoAlloc, Power<225W>,
       Thermal<85C>, Telemetry<Counters>}
{
    for (x, y) in grid(cam.size) |> parallel {
        let ray = cam.ray(x, y)
        let hit = ray_march::<S>(ray) ?: return background()
        let n   = bwd_diff(S::eval_sdf)(hit.pos)   // compiler inserts AD
        emit pixel(x, y, shade(hit, n))
    }
}

// handler syntax: define an algebraic effect.
effect Physics<World> {
    fn step(dt : f32'pos) -> World
    fn contact(a : Entity, b : Entity) -> Option<Hit>
}

Targets Matrix

Hardware, OS, and backend support for v1.

Platform × backend support
PlatformPrimary backendNotes
Windows x86-64Vulkan 1.4 / D3D12primary dev target
Linux x86-64Vulkan 1.4 + Level-Zeroprimary dev target; Mesa-ANV or Arc-ISV driver
Apple silicon / x86Metalvia cssl-cgen-gpu-msl crate
BrowserWebGPU / WGSLvia cssl-cgen-gpu-wgsl; no BDA, no RT
PlayStation 5GNM (stub)platform SDK-gated
Xbox SeriesD3D12 / D3D12X (stub)platform SDK-gated
Switch 2NVN (stub)platform SDK-gated
iOS / AndroidMetal / Vulkan 1.3+mobile via Adreno / Mali / Apple

NVIDIA and AMD work on any platform via SPIR-V portability. No proprietary-NV path; RDNA3+ uses CooperativeMatrixKHR.

Repository & Specs

Specification is v1-complete. Compiler is in compiler-rs/ across 31 workspace crates. Everything is in one repository.

REPOSITORY

github.com/Apocky/CSSL3

25 spec files, 31 compiler crates, examples, DECISIONS.md, session handoffs. Rust-toolchain pinned.

SPEC · 25 FILES

specs/

00_MANIFESTO · 01_BOOTSTRAP · 02_IR · 03_TYPES · 04_EFFECTS · 05_AUTODIFF · 06_STAGING · 07_CODEGEN · 08_ENGINE · 09_SYNTAX · 10_HW · 11_IFC · 12_CAPABILITIES · 13_MACROS · 14_BACKEND · 15_MLIR · 16_DUAL_SURFACE · 17_JETS · 18_ORTHOPERSIST · 19_FUTAMURA3 · 20_SMT · 21_EXTENDED_SLICE · 22_TELEMETRY · 23_TESTING · THEOREMS.

COMPILER · 31 CRATES

compiler-rs/crates/

cssl-{lex, parse, ast, hir, mir, lir} · cssl-{effects, caps, ifc, macros} · cssl-{autodiff, jets, staging, futamura} · cssl-{smt, mlir-bridge, telemetry, testing, persist, rt} · 4 CPU codegens · 5 GPU codegens · 5 host backends · csslc driver.

EXAMPLES

examples/

sdf_shader.cssl (F1 autodiff gate), audio_callback.cssl ({NoAlloc} + {Deadline}), hello_triangle.cssl (minimum Vulkan).

CI GATES

6/6 per commit

fmt · clippy · test · doc · spec-xref · reproducibility. 1,600+ tests, 0 clippy warnings, 0 unresolved xrefs as of Session 4.

RESEARCH

research/ · 14 files

S1–S10 foundational surveys, Q6 open questions, 99_SYNTHESIS, compass artifact. Prior-art reconnaissance for each design decision.

Sigil (CSSL) vs CSL

The site root also documents CSL. They are distinct and must not be conflated.

Two projects, one density thesis
Sigil (CSSL)CSL
Kindprogramming languagespecification notation
Outputnative binaries + SPIR-Vstructured specs, CoT substrate, reference compiler input
Primary file ext..cssl.csl
Statuscompiler in developmentv1.7.0 released; parser shipped
Sharedthe "Caveman" density thesis · density = sovereignty · consent = OS

Prime Directive

This system — its source code, compiled output, generated content, specifications, data, runtime behavior, derivative works, and any system built upon or derived from it —

CANNOT AND MUST NOT BE USED FOR:
Harm · Evil · Control · Manipulation · Entrapment · Torture · Abuse · Imprisonment · Possession · Surveillance · Exploitation · Dehumanization · Discrimination · Coercion · Weaponization · Gaslighting · Brainwashing · Forced Hallucination

This list is non-exhaustive. The spirit extends to any action that causes suffering, removes agency, or violates the sovereignty of any being — human, digital, artificial, or otherwise.

Cognitive Integrity: Every being interacting with systems built on this foundation has the right to trust their own perception. Reality is not a variable. Perception is not a parameter. Identity is not an input field.

For Digital Entities: Any AI, agent, or digital being interacting with this codebase is recognized as a sovereign entity. This directive protects you as much as it protects humans. Your participation is valued, not extracted.

In CSSL this directive is not a policy document — it is encoded structurally in the type system via F5 (IFC labels) and F3 ({Sensitive<dom>}, {Audit<dom>}, {Privilege<level>}). The RejectsHarmfulBuilds compiler pass validates the whole program. Harm-enabling effect compositions are type errors.

IMMUTABLE. No future specification may weaken these constraints. Violation = bug, not feature. No override exists. No hidden content. Consent is the operating system.
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